Digital RF multiplexing for a TVWS transceiver implementation

Future devices operating in the TV white space (TVWS) spectrum will require to access different bands at different locations and times in order to avoid interference to incumbent users, requiring agility and sufficient spectral masks to satisfy regulators. In order to realise radio devices capable of this, we briefly review design efforts on a radio transceiver capable up- and downconverting the 40 8MHz TVWS channels residing between 470MHz and 790MHz. While we briefly address the overall proposed structure, the aim of this contribution is to address the practical issues of interfacing data conversion devices sampling at RF to state-of-the-art FPGAs which can then perform the digital operations required for up- and downconversion

Efficient TV white space filter bank transceiver

Future devices operating in the TV white space (TVWS) spectrum will require to access different bands at different locations and times in order to avoid interference to incumbent users, requiring agility and sufficient spectral masks to satisfy regulators. Further, with very high-speed ADCs and DACs becoming reality, the purpose of this paper is to present a transceiver front-end capable of simultaneously up- and downconverting a significant portion of the UHF band. The proposed approach takes a two-stage filter-bank conversion for implementation on state-of-the-art FPGAs. We present three different parameterisations, which are compatible with the 40 TVWS channels between 470 and 790MHz in Europe, and compare them in terms of complexity and latency

TVWS filter bank transceiver on OMAP-L137 evaluation module

Communications devices operating in the TV white space (TVWS) spectrum will be strictly regulated, requiring compliance with spectral masks to protect incumbent users and sufficient frequency agility to allow access to numerous frequency bands at different times and locations. Therefore, future designs operating at radio frequency (RF) have been proposed. The purpose of this paper is to demonstrate an implementation of such a transceivers at a scale-down frequency implemented on the OMAP--L137 evaluation module, whereby the RF link can be replaced by the device's audio I/O, thus enabling easier observation and algorithm testing for students

Partially reconfigurable TVWS transceiver for use in UK and US markets

With more and more countries opening up sections of unlicensed spectrum for use by TV White Space (TVWS) devices, the prospect of building a device capable of operating in more than one world region is appealing. The difficulty is that the locations of TVWS bands within the radio spectrum are not globally harmonised. With this problem in mind, the purpose of this paper is to present a TVWS transceiver design which is capable of being reconfigured to operate in both the UK and US spectrum. We present three different configurations: one covering the UK TVWS spectrum and the remaining two covering the various locations of the US TVWS bands

Design considerations for a filter bank based TVWS transceiver

This paper discusses the design of a filter bank based transceiver capable of simultaneously up- or downconverting the entire TV white space (TVWS) frequency band. The spectral mask requirements favour a filter bank based approach, whereby RF sampling and the use of an FPGA for digital up- and down-conversion dictates a two-stage approach. Some of the design considerations, including filter design approaches, are discussed in this contribution

Wideband TV white space transceiver design and implementation

For transceivers operating in television white space (TVWS), frequency agility and strict spectral mask fulfilments are vital. In the UK, TVWS covers a 320 MHz wide frequency band in the UHF range, and the aim of this paper is to present a wideband digital up- and down converter for this scenario. Sampling at radio frequency (RF), a two stage digital conversion is presented, which consists of a polyphase filter for implicit upsampling and decimation, and a filter bank-based multicarrier approach to resolve the 8MHz channels within the TVWS band. We demonstrate that the up- and down-conversion of 40 such channels is hardly more costly than that of a single channel. Appropriate filter design can satisfy the mandated spectral mask and control the reconstruction error. An FPGA implementation is discussed, capable of running the wideband transceiver on a single Virtex-7 device with sufficient word length to preserve the spectral mask requirements of the system

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Inhalt: Regionale Aktivitäten: Klimabündnis Kieler Bucht erhält BMU-Förderung; Norddeutsche Regionalkonferenz; Neue Webseite informiert über Küstenschutzbedarf; RADOST-GIS präsentiert Indikatoren zur Gewässerqualität; Küstenforschung, Küstennutzung und Küstenschutz; Überregionale Aktivitäten: KLIMZUG-Abschlusskonferenz; Internationale Aktivitäten: HELCOM-Workshop in Warnemünde; RADOST auf dem Dupont Summit 2012; Publikationen: Ergebnisse der RADOST-Tour 2012; Integration des Klimawandels in die ökonomischen Analysen nach WRR

The Zynq Book : Embedded Processing with the Arm Cortex-A9 on the Xilinx Zynq-7000 All Programmable SoC

This book is about the Zynq-7000 All Programmable System on Chip, the family of devices from Xilinx that combines an application-grade ARM Cortex-A9 processor with traditional FPGA logic fabric. Catering for both new and experienced readers, it covers fundamental issues in an accessible way, starting with a clear overview of the device architecture, and an introduction to the design tools and processes for developing a Zynq SoC. Later chapters progress to more advanced topics such as embedded systems development, IP block design and operating systems. Maintaining a 'real-world' perspective, the book also compares Zynq with other device alternatives, and considers end-user applications. The Zynq Book is accompanied by a set of practical tutorials hosted on a companion website. These tutorials will guide the reader through first steps with Zynq

The Zynq Book Tutorials for Zybo and ZedBoard

This book comprises a set of five tutorials, and provides a practical introduction to working with Zynq-7000 All Programmable System on Chip, the family of devices from Xilinx that combines an application-grade ARM Cortex-A9 processor with traditional FPGA logic fabric. It is a companion text for 'The Zynq Book' (ISBN-13: 978-0992978709)

The Zynq Book (Chinese Version) : 基于含有ARM® Cortex®-A9 的Xilinx® Zynq®-7000 全可编程片上系统的嵌入式处理器

This book is about the Zynq-7000 All Programmable System on Chip, the family of devices from Xilinx that combines an application-grade ARM Cortex-A9 processor with traditional FPGA logic fabric. Catering for both new and experienced readers, it covers fundamental issues in an accessible way, starting with a clear overview of the device architecture, and an introduction to the design tools and processes for developing a Zynq SoC. Later chapters progress to more advanced topics such as embedded systems development, IP block design and operating systems. Maintaining a 'real-world' perspective, the book also compares Zynq with other device alternatives, and considers end-user applications. The Zynq Book is accompanied by a set of practical tutorials hosted on a companion website. These tutorials will guide the reader through first steps with Zynq, following on to a complete, audio-based embedded systems design